Seyed Reza Fatemi DATE:89/1/17 Ability to write VHDL code for Xilinx FPGA devices. Electrical background required so that programming is consistent with common electrical design practices. Good working understanding of circuits design. Familiarity with Xilinx FPGA toolset (including simulation). Also advantageous to have background in other programming languages such as Verilog or abel). Clocking and Control in a Multi-Partitioned, Scaled Architecture. Knowledge of clocking and timing techniques to develop modules that can be used for phase detection and common clocking across blades. Distributed Power Control. Knowledge and experience in distributed power control across multiple nodes in a scaled system. Education&Certification: Electronic Engineer From Caspin University 2008-2011 Tel:09123334584 Email:fatemi[at]altera.ir